With the spread of international digital communication networks, the CCITT (International Telegraph and Telephone Consultative Committee) has recommended a SDH (Synchronous Digital Hierarchy) as a rule for hierarchical channel multiplexing in a signal multiplex for digital communications, aiming at a mutual connection of digital communications.
The SDH multiplexes a module, called STM (Synchronous Transfer Module), to perform a digital communication. The CCITT made recommendations on various levels of STM, such as a STM-1 (Synchronous Transfer Module level 1, bit rate 155.52 Mb/s), STM-4 (Synchronous Transfer Module level 4, bit rate 622.08 Mb/s), and STM-16 (Synchronous Transfer Module level 16, bit rate 2.4883 Gb/s).
In particular, the SDH constitutes a multiplex communication system to be based on for introduction of an ATM (asynchronous transfer mode) which is one of important techniques in construction of recent wide-band communication networks.
As a conventional synchronous multiplex converter coping with such a communication system, for example, there is disclosed a “synchronism detection circuit” (or synchronoscope) in Japanese Patent Application Laid-Open Publication No. 5-175953. FIG. 8 shows, in block diagram, a schematic arrangement of the conventional synchronism detection circuit, as a circuit adapted for synchronous detection to be performed in particular of a multiplexed signal at the above-noted STM-4.
This conventional synchronism detection circuit is constituted with a bit serial-parallel conversion circuit 701 that converts a serial STM-4 multiplexed signal 705 into an 8-bit parallel STM-4 multiplexed signal, a byte serial-parallel conversion circuit 702 that converts the multiplexed signal 706 into four 8-bit parallel STM-1 signals 707a, 707b, 707c, and 707d, first to fourth frame pattern detection circuits 731, 732, 733, and 734 that detect respective frame patterns of the tributary STM-1 signals 707a, 707b, 707c, and 707d to output bit shift signals 701a, 702a, 703a, and 704a and frame pattern detection signals 701b, 702b, 703b, and 704b, a bit shift control circuit 708 responsible for the bit shift signals 701a, 702a, 703a, and 704a input from the respective frame pattern detection circuits 731, 732, 733, and 734 to output a bit shift command 709a to the bit serial-parallel conversion circuit 701, a synchronism control circuit 704 responsible for the frame pattern detection signals 701b, 702b, 703b, and 704b input from the respective frame pattern detection circuits 731, 732, 733, and 734 to output a tributary shift command 704j to the byte serial-parallel conversion circuit 702, and a logical product circuit 709 to which outputs of the bit shift control circuit 708 and the synchronism control circuit 704 are input.
How this synchronism detection circuit functions will now be explained. First, the frame pattern detection circuits 731 to 734 are operated, for each of STM-1 signals 707a to 707d after a multi-division by the byte serial-parallel conversion circuit 702, that is, for each tributary, to detect a bit shift of that STM-1 signal, to thereby output bit shift signals 701a to 704a to the bit shift control circuit 708.
The bit shift control circuit 708 decides if values of the bit shift signals 701a to 704a match each other, and responds to any match at a value other than 0, by giving a bit advance decision signal 708b to be sent to the synchronism control circuit 704 and a concurrent pulse 708a, corresponding to its value, to be sent to the logical product circuit 709.
On the other hand, at the synchronism control circuit 704, there are input frame pattern detection signals 701b to 704b that are output from the respective frame pattern detection circuits 731 to 734. The synchronism control circuit 704 performs, on basis of the frame pattern detection signals 701b to 704b, a checking judgment for a slip of their tributary synchronization to thereby output a tributary shift command 704j, as a pulse corresponding to the slip, to the byte serial-parallel conversion circuit 702.
Further, the synchronism control circuit 704 is responsible for combination of the frame pattern detection signals 701b to 704b and the bit advance decision signal 708b output from the bit shift control circuit 708, to detect a slipped state of synchronism to thereby send a synchronism slip signal 704k to the logical product circuit 709. Therefore, the logical product circuit 709 inputs thereto the pulse 708a indicating a bit advance value and the synchronism slip signal 704k, and outputs a result of operation of a logical product between them to the bit serial-parallel conversion circuit 701, which means that the bit serial-parallel conversion circuit 701 has, in a synchronism slipping state, a bit shift command 709a input thereto.
Accordingly, the bit serial-parallel conversion circuit 701 and the byte serial-parallel conversion circuit 702 input thereto the bit shift command 709a and the tributary shift command 704j, respectively, and respond thereto by synchronism pull-in actions to establish a tributary synchronization.
The conventional synchronism detection circuit, however, detects a tributary slip amount based on the timing of occurrences of the frame pattern detection signals 701b to 704b, and inputs a pulse corresponding to the amount as the tributary shift command 704j to the byte serial-parallel conversion circuit 702, to thereby achieve a correction of tributary slip, and as a premise, it is necessary for respective tributary frame bits to be matching upon reception of the serial STM-4 multiplexed signal 705.
FIG. 9 describes, by illustration, positions of frame bits contained in data associated with actions of the conventional synchronism detection circuit. As shown in FIG. 9, at the end of a transmitter cooperating with a receiver, which has the above-noted synchronism detection circuit installed therein, to constitute a data transmission and reception system, tributary signals 801a, 801b, 801c, and 801d have frame bits 802 simultaneously inserted therein. Therefore, in a signal 803 multiplexed by a parallel-serial conversion, frame bits of the tributary signals are disposed in specified positions.
Then, upon a serial-parallel conversion at the receiver end, the frame bits of tributary signals have their slipped positions in dependence on their timing of the conversion. The synchronism detection circuit described detects bit slips of the tributary signals to thereby make a decision for tributary signals to be inherently distributed, information whereof is based on for timing adjustment of the serial-parallel conversion circuit to achieve a tributary synchronization.
It is therefore necessary for implementation of a tributary synchronization at the conventional synchronism detection circuit to output tributary signals with frame bits matching in phase at the transmitter end.
However, with an increased speed in terms of bit rate in communication, it has become impossible to neglect a phase skew of parallel signals due to a phase dispersion of devices, as well as dispersions in production or application. In a probable case such that with a still increased communication speed the phase dispersion of frames between tributary signals has a phase difference of 1 bit or more, it will become difficult as a problem for a parallel-serial conversion to be performed, at a parallel-serial conversion circuit in the transmitter, with frames of tributary signals matching in phase.
Further, in the data transmission and reception system in which the above-noted synchronism detection circuit is introduced in the receiver, if a multiplexed signal with frames slipped in phase between tributary signals is subjected as it is to the parallel-serial conversion for transmission at the transmitter end, then the receiver will fail to make a proper tributary synchronization, so that the original signal cannot be reproduced.